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> Informasic launches the XTEA core for integration of encryption in FPGA and ASIC |
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Monday, 28 August 2006 |
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The flexible and highly scalable
InformAsic XTEA core makes it possible to add encryption into FPGA
and ASIC designs. The core requires minimal hardware resources and is
hence suitable for designs where resource intensive algorithms, like
AES and 3DES does not fit.
The InformAsic XTEA core implements the
XTEA (Extended Tiny Encryption Algorithm) block cipher. This cipher
is suitable for embedded solutions where good security with a small
footprint is needed. The cipher uses a 128 bit key and works on blocks
of 64 bits. The core implements ECB mode; other
modes can be provided upon request.
The core provides the ability to
balance between performance and security by at compile time select
the number of rounds to be performed on a given block, however it is
recommended to perform at least 24 rounds, says Joachim Strömbergson,
CTO at InformAsic.
The core is suitable for embedded
systems with moderate bandwidth requirements, i.e. up to 100 Mbit/s.
. . The core features a very fast two cycle only setup time and the
core will complete a round in two cycles. For a 32 round operation
the total latency will be 66 cycles. All inputs and outputs are
registered. The design uses no memory blocks, multipliers or DSP
functions and uses a single positive edge triggered clock and a
single synchronous, active low reset.
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