Implementation of a format translator. Industry: Security

Challenge:
Develop an IP Core that implements a format translator with support for multiple video streams and a bandwith of 800 MByte/s.

• Description:
• * RTL-development using SystemVerilog
• * Development of a test environment
• * Verification with SystemVerilog-assertions including test cases executed on a processor model
• * Development of a regression suite for continously unit testing
• 
  

• Tools, methods and technology:
• * SystemVerilog as RTL-language
• * Synopsys VCS for functional verification
• * Synthesis with Synopsys Design Compiler
• * Subversion for version control management
• * Processor based verification
• 
  

• Resultats:
• An IP-core ready to be integrated in an ASIC