Adaption and optimization of a processor core for a new system on chip (SoC) to meet performance and power consumption requirements. Industry: Consumer Products

• Description:
• * RTL-development of a new memory system with access priorities
• * RTL-development of a new I/O-system with support for several streams
• * Development of test code for functions testing
• * Development of test cases, performance and power consumption measurement
• * Optimizing power consumption and implementation of a clock strategy

• Tools, methods and technology:
• * 32-bit processor core from the ARC 700-family
• * TSMC 180 nm process with Virage Logic ultra low power lib process
  
• * 1TSRAM-memories
• * Controlling synchronization of individual registers
• * Cadence BuildGates Extreme for synthesesis
• * NC-Verilog for verification
• * Verilog 2001 as design language
• * Subversion for version control management
• * Eclipse with GCC and ARC's assembler system for SW-development
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• Resultats:
• * Processor core with a new memory system and application adapted I/O system supporting mulitple streams
• * Power consumption for application code reduced by 25%
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