We usually work with the ASIC front end design, but we also have experience with back end design processes such as floor planning, place&route and statistic timing analysis. The technology processes we have been working on in our different projects covers 350 - 65nm from NEC, Wafertech, ST, IBM, LSI Logic, Samsung and UMC.

Development tools we have been using in ASIC design processes are MathLab, SimuLink, Cossap, SystemC, VHDL, Renoir, Eclipse, ModelSim, VCS, NC-Sim, NC-Verilog, Synopsis, DC, Physopt BuildGates/PKS/Extreme, Get2Chip, Blastfusion. See below.

The tools we are using when designing ASICs are: